1. Incorporation by Reference
Co-pending application, patent application Ser. No. 08/742,603, issued as U.S. Pat. No. 5,896,492 on Apr. 20, 1996 hereby incorporated by reference in its entirety.
2. Field of the Invention
This invention relates to the field of data transfers in a computer system. More particularly, the present invention relates to streamlining data transfers using the existing bandwidth in the computer system.
3. Description of the Related Art
The proliferation of high data retrieval rate applications such as on-demand video servers has resulted in a corresponding need for computer systems which have reliable mass storage systems capable of high bit-rate transfers. FIG. 1 is a block diagram of a conventional computer system 100 which includes a host processor 110, a host memory 105, a memory controller 120 and a bank of memory devices 141, 142, 143 and 144, e.g., disk drives. The inclusion of memory controller 120 provides partial relief to the processing load of host processor 110 by offloading the burden of the device-level read/write steps required for transferring data to/from drives 141, 142, 143, 144.
For example, to initiate a read operation, host processor 110 simply sends a controller read command to controller 120 and then waits for a corresponding controller data packet from controller 120. As a result, host processor 110 can be freed up quickly to support other processes while the controller 120 retrieves the data from drives 141, 142, 143, 144. Upon receiving the controller read command, controller 120 translates the controller read command into a number of device read commands, which are then issued to the corresponding drives 141, 142, 143, 144.
Referring now to FIG. 2, in response to the device read commands, drives 141, 142, 143, 144 form device data packets 241, 242, 243, 244, respectively, all the device data packets destined for controller 120. Note that read data R1, R2, R3, and R4 represent the respective requested data from drives 141, 142, 143, 144. Controller 120 stores data R1, R2, R3, R4 in controller cache 125. Next, controller 120 forms a corresponding number of controller data packets 221, 222, 223, 224 destined for host processor 110, which includes data R1, R2, R3 and R4, respectively.
Referring now to FIG. 3, to initiate a write operation, host processor 110 sends a number of controller data packets 311, 312, 313, 314, destined for controller 120. Controller 120 is now responsible for ensuring that the write data W1, W2, W3 and W4 arrive at their respective final destinations, i.e., arrive at drives 141, 142, 143, 144. First, controller 120 copies the write data W1, W2, W3, W4 into controller cache 125. Controller 120 then forms a corresponding number of device data packets 331, 332, 333, 334 and issues them to drives 141, 142, 143, 144, respectively.
Unfortunately, in the conventional read and write operations described above, the penalty for offloading the device-level steps from host processor 110 causes controller 120 to temporarily store the read/write data in cache 125. As a result, the bandwidth requirement on interconnect 182 is twice the underlying bit-rate needed for transferring data from host processor 110 to memory 140 without the use of any memory controller.
Hence, there is a need for an efficient scheme for storing and retrieving data which offloads the host processor without requiring a significant increase in bandwidth of the system interconnect.